The present invention relates to a logic analyzer which applies test pattern signals to a circuit under test, sequentially reads the output data therefrom into a memory and reads out therefrom the data for analysis or display.
Heretofore there has been proposed in, for example, U.S. Pat. Nos. 4,425,643 and 4,434,488, a logic analyzer which reads waveform outputs occurring at respective parts of a logic circuit and displays output waveforms from which the operator judge whether the logic circuit is correctly operating or not. With this kind of logic analyzer, since the operator passes judgement on the operation of the circuit under test on the basis of the timing of the plurality of logic waveforms being displayed, he is required to be well versed in the operation of the circuit under test. Accordingly, much skill is needed for the test using such a logic analyzer.
Recently there has come into use a logic analyzer of the type that applies a test pattern signal from a simple pattern generator to the circuit under test and obtains the response output therefrom for observation, and that perform in analysis or comparison with an expected value so as to judge whether the circuit under test is non-defective or defective.
The test pattern signal must be chosen properly in accordance with the function of the circuit under test. For example, a logic circuit performing a counting operation and a logic circuit performing a logic operation entirely differ in the flow of the test pattern signal. Therefore, in the case where the circuit under test includes, for example, a counting operation part and a logic operation part and repeats an operation such that, for instance, when the count value reaches a certain value, a certain logic operation circuit operates and the counter operates again based on the logic operation result, it is necessary that the test pattern signal generating condition of the pattern generator differ depending upon which of the counter and the logic operation circuit is in operation. Further, there are cases where the test pattern signal generating parameters are changed when a certain malfunction is detected during the test of a circuit having one function.
To meet the abovesaid requirements, there has been proposed such a method that when the logic state of the circuit under test reaches a predetermined logic state, a signal indicating this is produced and used as an interrupt signal to thereby change the test pattern signal generating parameters. In some cases, however, the time when the circuit under test is put in the predetermined logic state varies under the influence of an external signal, or the circuit is repeatedly put in the predetermined logic state. Therefore, the above interruption system has the disadvantage that when the circuit under test satisfies the predetermined logic condition, even if the pattern generator is executing a program of generating a series of test pattern signals, the flow of generation of the test pattern signals is changed over. That is, predetermined kinds of test pattern signals are applied from the pattern generator to the circuit under test all to test its functions, but if the generation of a certain series of test pattern signals is switched to the generation of another series of test pattern signals, then the circuit under test cannot be completely tested.
Since the logic analyzer is used for testing a logic circuit, it is required to permit free setting of the waveform of the test pattern signal. Namely, the logic analyzer is designed to permit freely setting, as the test pattern signal waveform, an NRZ or RZ waveform and, in the case of the latter, its polarity, delay time .tau..sub.D relative to the reference timing and pulse width .tau..sub.W.
Conventionally, when the conditions of the waveform of each test pattern signal to be generated are set, the polarity is displayed in the form of a symbol and the delay time .tau..sub.D and the pulse width .tau..sub.W in numerical form. Accordingly, it is impossible for the operator to intuitively know what test pattern signals have been set. Accordingly, the operator has to imagine the waveforms of a plurality of test pattern signals to be generated and their mutual phase relationships from the displayed numeric values and symbols, so as to judge whether the waveform conditions being set are appropriate or not. When two or three kinds of test pattern signals are to be generated, the waveform conditions can be set without much difficulty, but as the number of types of test pattern signals to be generated increases, it becomes more and more difficult for the operator to imagine what waveforms the test pattern signals will assume and what phase relationships they will bear. Therefore, the waveform conditions of the test pattern signals cannot easily be set.